? october 2000 1/10 VNA7NV04D aomnifet iio: fully autoprotected power mosfets target specification 1 n linear current limitation n thermal shut down n short circuit protections n integrated clamp n low current drawn from input pins n diagnostic feedback through input pins n esd protection n direct access to the gate of each power mosfet (analog driving) n compatible with standard power mosfets description the VNA7NV04D is a device | formed by two | monolithic omnifet ii chips housed in a standard so-16 package with double island. the omnifet ii are designed in stmicroelectronics vipower m0 technology; they are intended for replacement of standard power mosfets from dc up to 50khz applications. built in thermal shutdown, linear current limitation and overvoltage clamp protect the chips in harsh environments. fault feedback can be detected by monitoring the voltage at the input pins. type r ds(on) i lim v clamp VNA7NV04D 60 m w (*) 6 a (*) 40 v (*) so-16 (double island) block diagram source2 overvoltage linear drain1 source1 clamp current limiter over temperature gate control drain2 overvoltage clamp linear current limiter gate control over temperature input2 input1 (*) per each device
2/10 VNA7NV04D absolute maximum rating (per each device) connection diagram (top view) current and voltage conventions symbol parameter value unit v ds drain-source voltage (v in =0v) internally clamped v v in input voltage internally clamped v i in input current +/- 20 ma i d drain current internally limited a i r reverse dc output current - 12 a v esd electrostatic discharge (r=1.5k w ; c=100pf) 4000 v p tot total dissipation at t c =25 c tbd w t j operating junction temperature internally limited c t c case operating temperature internally limited c t stg storage temperature -55 to 150 c 1 drain 1 input 1 source 2 i in1 v in1 input 2 i in2 source 1 drain 2 v in2 i d2 i d1 v ds1 v ds1 input 2 source 2 source 2 source 2 input 1 drain 1 drain 1 drain 1 drain 2 drain 2 drain 2 n.c. source 1 n.c. source 1 source 1 1 8 9 16
3/10 VNA7NV04D thermal data electrical characteristics (per each device) -40 c< t j < 150 c, unless otherwise specified off on dynamic switching symbol parameter value unit r thj-case thermal resistance junction-case max 13 c/w r thj-amb thermal resistance junction-ambient max tbd c/w symbol parameter test conditions min typ max unit v clamp drain-source clamp voltage v in =0v; i d =3.5a 40 45 50 v v clth drain-source clamp threshold voltage v in =0v; i d =2ma 36 v v inth input threshold voltage v ds =v in; i d =1ma 0.5 2.5 v i iss supply current from input pin v ds =0v; v in =5v 100 250 m a v incl input-source clamp voltage i in =1ma i in =-1ma 6.5 -1.0 7.4 8.5 -0.3 v i dss zero input voltage drain current (v in =0v) v ds =13v; v in =0v; t j =25 c v ds =25v; v in =0v 50 150 m a symbol parameter test conditions min typ max unit r ds(on) static drain-source on resistance v in =5v; i d =3.5a; t j =25 c v in =5v; i d =3.5a 60 120 m w symbol parameter test conditions min typ max unit g fs (*) forward transconductance v dd =13v; i d =3.5a 10 s c oss output capacitance v ds =13v; f=1mhz; v in =0v 230 pf symbol parameter test conditions min typ max unit t d(on) turn-on delay time v dd =15v; i d =3.5a v gen =5v; r gen =10 w (see figure 1) 40 tbd ns t r rise time 100 tbd ns t d(off) turn-off delay time 250 tbd ns t f fall time 90 tbd ns t d(on) turn-on delay time v dd =15v; i d =3.5a v gen =5v; r gen =1000 w (see figure 1) 0.6 tbd m s t r rise time 4.7 tbd m s t d(off) turn-off delay time 7.6 tbd m s t f fall time 4.6 tbd m s (di/dt) on turn-on current slope v dd =15v; i d =3.5a v gen =5v; r gen =0 w 28 a/ m s q i total input charge v dd =12v; i d =3.5a; v in =5v (see figure 5) tbd nc 1
4/10 VNA7NV04D electrical characteristics (continued) (t j =25 c, unless otherwise specified) source drain diode protections (-40 c 5/10 VNA7NV04D protection features (per each device) during normal operation, the input pin is electrically connected to the gate of the internal power mosfet through a low impedance path. the device then behaves like a standard power mosfet and can be used as a switch from dc up to 50khz. the only difference from the user's standpoint is that a small dc current i iss (typ. 100 m a) flows into the input pin in order to supply the internal circuitry. the device integrates: - overvoltage clamp protection: internally set at 45v, along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. this feature is mainly important when driving inductive loads. - linear current limiter circuit: limits the drain current i d to i lim whatever the input pin voltages. when the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . - overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cutout occurs in the range 150 to 190 c, a typical value being 170 c. the device is automatically restarted when the chip temperature falls of about 15 c below shut-down temperature. - status feedback: in the case of an overtemperature fault condition (t j >t jsh ), the device tries to sink a diagnostic current i gf through the input pin in order to indicate fault condition. if driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. if the drive impedance is high enough so that the input pin driver is not able to supply the current i gf , the input pin will fall to 0v. this will not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current i iss . additional features of this device are esd protection according to the human body model and the ability to be driven from a ttl logic circuit. 1
6/10 VNA7NV04D 1 fig.2: test circuit for diode recovery times (per single chip) fig.1: switching time test circuit for resistive load (per single chip) r gen v gen v d t i d 90% 10% t v gen t d(on) t d(off) t f t r l=100uh a b 8.5 w v dd r gen fast diode omnifet a d i s 25 w b omnifet d s i v gen
7/10 VNA7NV04D 1 fig. 3: unclamped inductive load test circuits (per single chip) fig. 4: unclamped inductive waveforms (per single chip) fig. 5: input charge test circuit (per single chip) gen nd8003 v in
8/10 VNA7NV04D 1 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.004 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 9.8 10 0.385 0.393 e 5.8 6.2 0.228 0.244 e 1.27 0.050 f 3.8 4.0 0.149 1.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.62 0.024 s8 (max.) so-16 mechanical data
9/10 VNA7NV04D 1 so-16 tube shipment (no suffix) 1 all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 3.2 b 6 c( 0.1) 0.6 tape and reel shipment (suffix a13tro) all dimensions are in mm. base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions c b a
10/10 VNA7NV04D information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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